Template:EXT1 connector HOST side pinout
From fit-PC wiki
EXT-1 connector HOST side | |||||
---|---|---|---|---|---|
Pin # | Pin Name | Signal Description | Pin # | Pin Name | Signal Description |
A1 | GND | Ground connection | B1 | GND | Ground connection |
A2 | SATA2_TX+ | SATA2.0 differential transmit pair 2; Host signal shared with mini PCIe (MUX channel B) | B2 | SATA0_TX+/CLK+ | Host PEG CLK output differential pair - 100MHz PCIe Gen2 to PCIe Graphics device1 |
A3 | SATA2_TX- | B3 | SATA0_TX-/CLK- | ||
A4 | IR_RX | IR UART receive signal | B4 | SATA0_LED | SATA activity LED indicator |
A5 | SATA2_RX+ | SATA2.0 differential receive pair 2; Host signal shared with mini PCIe (MUX channel B) 3 | B5 | SATA0_RX+/CLK+ | Host PCIe CLK output differential pair - 100MHz PCIe Gen2 to PCIe devices1 |
A6 | SATA2_RX- | B6 | SATA0_RX-/CLK- | ||
A7 | GND | Ground connection | B7 | V5SBY | 5V power domain |
A8 | SATA3_TX+ | SATA2.0 differential transmit pair 33 | B8 | SATA1_RX+ | SATA3.0 differential receive pair 12 |
A9 | SATA3_TX- | B9 | SATA1_RX- | ||
A10 | SMB_ALRT# | SMBus Alert used to wake the system | B10 | DEBUG1 | Reserved debug signal |
A11 | SATA3_RX+ | SATA2.0 differential receive pair 33 | B11 | SATA1_TX+ | SATA3.0 differential transmit pair 12 |
A12 | SATA3_RX- | B12 | SATA1_TX- | ||
A13 | V5SBY | 5V power domain | B13 | V5SBY | 5V power domain |
A14 | SMB_CLK | SMBus host clock output. Connect to SMBus slave. | B14 | USB3_P | USB Host interface 3 |
A15 | SMB_DAT | SMBus bidirectional data. Connect to SMBus slave. | B15 | USB3_N | |
A16 | HDA_RST# | High Definition Audio host reset | B16 | USB_OC_2_3# | USB Overcurrent Indicator for lanes 2/3 |
A17 | HDA_SYNC | High Definition Audio host sync | B17 | USB2_P | USB Host interface 2 |
A18 | HDA_BITCLK | High Definition Audio host bit clock out 24MHz | B18 | USB2_N | |
A19 | HDA_SDOUT | High Definition Audio serial host data out | B19 | V5SBY | 5V power domain |
A20 | HDA_SDIN1 | High Definition Audio serial host data in1 | B20 | COM2_RX | For internal test purposes |
A21 | HDA_SDIN0 | High Definition Audio
serial host data in0 |
B21 | COM2_TX | For internal test purposes |
A22 | DEBUG3 | Reserved debug signal | B22 | LPC_SERIRQ | Serial Interrupt Request |
A23 | GND | Ground connection | B23 | LPC_CLK | Single Ended 33MHz CLK host out to PCI devices |
A24 | USB0_P | USB Host interface lane 0 | B24 | LPC_FRAME# | LPC interface frame signal |
A25 | USB0_N | B25 | GND | Ground connection | |
A26 | USB_OC0_1# | USB Overcurrent Indicator
for lanes 0/1 |
B26 | SPI_MISO | SPI interface MISO signal – Reserved for internal use only |
A27 | USB1_P | USB Host interface 1 | B27 | SPI_MOSI | SPI interface MOSI signal – Reserved for internal use only |
A28 | USB1_N | B28 | SPI_CLK | SPI interface Clock signal – Reserved for internal use only | |
A29 | GND | Ground connection | B29 | SPI_CS1# | SPI interface chip select 1 – Reserved for internal use only |
A30 | LPC_AD0 | LPC bus multiplexed
command, address and data. Internal PU provided on LPC[3:0] |
B30 | SPI_CS0# | SPI interface chip select 0 – Reserved for internal use only |
A31 | LPC_AD1 | B31 | RESET# | Active Low Platform Reset driven by the Host | |
A32 | LPC_AD2 | B32 | PCIE_CLK+ | Host PCIe CLK output differential pair - 100MHz PCIe Gen2 to PCIe devices | |
A33 | LPC_AD3 | B33 | PCIE_CLK- | ||
A34 | GND | Ground connection | B34 | EXT_PRSNT# | Clock Request for PCI Express 100 MHz Clocks |
A35 | PCIE_TX3+ | PCI Express (x1) Gen2 (up
to 5Gbps) differential transmit pair 3 |
B35 | PCIE_RX3+ | PCI Express (x1) Gen2 (up to 5Gbps) differential receive pair 3 |
A36 | PCIE_TX3- | B36 | PCIE_RX3- | ||
A37 | PCIE_WAKE# | PCI Express Wake Event from Device to Host | B37 | SPI_EXT_CNTRL | SPI interface external control signal |
A38 | PCIE_TX2+ | PCI Express (x1) Gen2 (up to 5Gbps) differential transmit pair 2 | B38 | PCIE_RX2+ | PCI Express (x1) Gen2 (up to 5Gbps) differential receive pair 2 |
A39 | PCIE_TX2- | B39 | PCIE_RX2- | ||
A40 | GND | Ground connection | B40 | GND | Ground connection |
A41 | PCIE_TX1+ | PCI Express (x1) Gen2 (up to 5Gbps) differential transmit pair 1 | B41 | PCIE_RX1+ | PCI Express (x1) Gen2 (up to 5Gbps) differential receive pair 1 |
A42 | PCIE_TX1- | B42 | PCIE_RX1- | ||
A43 | PWRBTN# | System power button signal | B43 | SLP# | Assert LP state S3 (sleep) active low signal |
A44 | PCIE_TX0+ | Host CPU PEG (x1) - PCIe Gen3 (up to 8Gbps) differential transmit pair for external graphics | B44 | PCIE_RX0+ | Host CPU PEG (x1) - PCIe Gen3 (up to 8Gbps) differential receive pair for external graphics |
A45 | PCIE_TX0- | B45 | PCIE_RX0- | ||
A46 | RESERVED | Reserved debug signal | B46 | RESERVED | Reserved debug signal |
A47 | VCC_12V | Main 12V power domain | B47 | VCC_12V | Main 12V power domain |
A48 | VCC_12V | B48 | VCC_12V | ||
A49 | VCC_12V | B49 | VCC_12V | ||
A50 | VCC_12V | B50 | VCC_12V |