Changes
| A2
| PEG_RX0+/RSVD0
| rowspan="2" | Host CPU PEG_0 (x8) - PCIe Gen3 (up to 8Gbps) differential receive pair for external graphics (note 1).
| B2
| PEG_TX0+/RSVD6
| rowspan="2" | Host CPU PEG_0 (x8) - PCIe Gen3 (up to 8Gbps) differential transmit pair for external graphics (note 1).
|-
| A3
| A5
| PEG_RX1+/RSVD4
| rowspan="2" | Host CPU PEG_1 (x8) - PCIe Gen3 (up to 8Gbps) differential receive pair for external graphics (note 1).
| B5
| PEG_TX1+/RSVD9
| rowspan="2" | Host CPU PEG_1 (x8) - PCIe Gen3 (up to 8Gbps) differential transmit pair for external graphics (note 1).
|-
| A6
| A8
| PEG_RX2+/RSVD11
| rowspan="2" | Host CPU PEG_2 (x8) - PCIe Gen3 (up to 8Gbps) differential receive pair for external graphics (note 2).
| B8
| PEG_TX2+/RSVD16
| rowspan="2" | Host CPU PEG_2 (x8) - PCIe Gen3 (up to 8Gbps) differential transmit pair for external graphics (note 2).
|-
| A9
| A10
| DGPU_PWROK/RSVD13
| Host chipset GPIO17, Input/Output, PD-10k
| B10
| DGPU_HOLD_RST#/RSVD18
| A11
| PEG_RX3+/RSVD14
| rowspan="2" | Host CPU PEG_3 (x8) - PCIe Gen3 (up to 8Gbps) differential receive pair for external graphics (note 2).
| B11
| PEG_TX3+/RSVD19
| rowspan="2" | Host CPU PEG_3 (x8) - PCIe Gen3 (up to 8Gbps) differential transmit pair for external graphics (note 2).
|-
| A12
| A14
| PEG_RX4+/RSVD21
| rowspan="2" | Host CPU PEG_4 (x8) - PCIe Gen3 (up to 8Gbps) differential receive pair for external graphics (note 2).
| B14
| PEG_TX4+/RSVD26
| rowspan="2" | Host CPU PEG_4 (x8) - PCIe Gen3 (up to 8Gbps) differential transmit pair for external graphics (note 2).
|-
| A15
| A17
| PEG_RX5+/RSVD24
| rowspan="2" | Host CPU PEG_5 (x8) - PCIe Gen3 (up to 8Gbps) differential receive pair for external graphics (note 2).
| B17
| PEG_TX5+/RSVD29
| rowspan="2" | Host CPU PEG_5 (x8) - PCIe Gen3 (up to 8Gbps) differential transmit pair for external graphics (note 2).
|-
| A18
| A20
| PEG_RX6+/RSVD31
| rowspan="2" | Host CPU PEG_6 (x8) - PCIe Gen3 (up to 8Gbps) differential receive pair for external graphics (note 2).
| B20
| PEG_TX6+/RSVD36
| rowspan="2" | Host CPU PEG_6 (x8) - PCIe Gen3 (up to 8Gbps) differential transmit pair for external graphics (note 2).
|-
| A21
| A23
| PEG_RX7+/RSVD34
| rowspan="2" | Host CPU PEG_7 (x8) - PCIe Gen3 (up to 8Gbps) differential receive pair for external graphics (note 2).
| B23
| PEG_TX7+/RSVD38
| rowspan="2" | Host CPU PEG_7 (x8) - PCIe Gen3 (up to 8Gbps) differential transmit pair for external graphics (note 2).
|-
| A24
| A26
| LVDS_A0+/eDP_TX0+
| rowspan="2" | LVDS Channel A differential pair 0 Host data output 3
| B26
| PEG_CLK+/RSVD40
| rowspan="2" | Host PEG CLK output differential pair - 100MHz PCIe Gen2 to PCIe Graphics device
|-
| A27
| A28
| LVDS_A1+/eDP_TX1+
| rowspan="2" | LVDS Channel A differential pair 1 Host data output 3
| B28
| LVDS_BKLT_CTRL
| Panel Backlight Brightness Control 3
|-
| A29
| A30
| LVDS_A2+/eDP_TX2+
| rowspan="2" | LVDS Channel A differential pair 2 Host data output 3
| B30
| COM1_TX
| A33
| LVDS_A3+/eDP_TX3+
| LVDS Channel A differential pair 3 Host data output 3
| B33
| COM1_DTR
| rowspan="5" | Full RS232 interface from Host to DCE device
|-
| A34
| A36
| LVDS_ACLK+/eDP_AUX+
| LVDS Channel A differential pair Host clock output 3
| B36
| COM1_CTS
| A39
| LVDS_CTRL_CLK
| LVDS Control interface for external SSC clock chip (I2C based). Optional. 3
| B39
| LVDS_I2C_CLK
| LVDS DDC (I2C based) management interface. EDID support for flat panel display 3
|-
| A40
| A41
| PEG_CLK_REQ#/RSVD42
| Clock Request Signal for PCIe Graphics (PEG)
| B41
| GND
| A47
| USB_OC_4_5#
| USB Overcurrent Indicator for lanes 2/3
| B47
| SPARE0
| VCC_12V
|}
Notes:
# Merged with PCI Express signals to Mini PCIe card on fit-PC3/3i
# GPIOs on fit-PC3/3i
# Fit-PC3/3i design does not feature LVDS interface
