Difference between revisions of "Template:EXT1 connector HOST side pinout"

From fit-PC wiki
Jump to: navigation, search
 
(10 intermediate revisions by the same user not shown)
Line 1: Line 1:
 
{| style="width: 100%; height: 200px;" border="1" cellpadding="10" cellspacing="0" align="center"
 
{| style="width: 100%; height: 200px;" border="1" cellpadding="10" cellspacing="0" align="center"
−
|- style="vertical-align:middle;"
+
! colspan="6" | EXT-1 connector HOST side
−
! colspan="6" style="text-align: center; font-weight: bold;" | EXT-1 connector HOST side
+
 
|-
 
|-
 
| Pin #
 
| Pin #
Line 19: Line 18:
 
| A2
 
| A2
 
| SATA2_TX+
 
| SATA2_TX+
−
| SATA2.0 differential transmit pair 2; Host signal shared with mini PCIe (MUX channel B)
+
| rowspan="2" | SATA2.0 differential transmit pair 2; Host signal shared with mini PCIe (MUX channel B)
 
| B2
 
| B2
 
| SATA0_TX+/CLK+
 
| SATA0_TX+/CLK+
−
| Host PEG CLK output differential pair - 100MHz PCIe Gen2 to PCIe Graphics device1
+
| rowspan="2" | Host PEG CLK output differential pair - 100MHz PCIe Gen2 to PCIe Graphics device1
 
|-
 
|-
 
| A3
 
| A3
Line 28: Line 27:
 
| B3
 
| B3
 
| SATA0_TX-/CLK-
 
| SATA0_TX-/CLK-
−
|
 
−
|
 
 
|-
 
|-
 
| A4
 
| A4
Line 36: Line 33:
 
| B4
 
| B4
 
| SATA0_LED
 
| SATA0_LED
−
| SATA activity LED
+
| SATA activity LED indicator
−
  indicator
+
 
|-
 
|-
 
| A5
 
| A5
 
| SATA2_RX+
 
| SATA2_RX+
−
| SATA2.0 differential receive pair 2; Host signal shared with mini PCIe (MUX channel B) 3
+
| rowspan="2" | SATA2.0 differential receive pair 2; Host signal shared with mini PCIe (MUX channel B). Note 3
 
| B5
 
| B5
 
| SATA0_RX+/CLK+
 
| SATA0_RX+/CLK+
−
| Host PCIe CLK output differential pair - 100MHz PCIe Gen2 to PCIe devices1
+
| rowspan="2" | Host PCIe CLK output differential pair - 100MHz PCIe Gen2 to PCIe devices. Note 1
 
|-
 
|-
 
| A6
 
| A6
Line 50: Line 46:
 
| B6
 
| B6
 
| SATA0_RX-/CLK-
 
| SATA0_RX-/CLK-
−
|
 
−
|
 
 
|-
 
|-
 
| A7
 
| A7
Line 62: Line 56:
 
| A8
 
| A8
 
| SATA3_TX+
 
| SATA3_TX+
−
| SATA2.0 differential transmit pair 33
+
| rowspan="2" | SATA2.0 differential transmit pair 33
 
| B8
 
| B8
 
| SATA1_RX+
 
| SATA1_RX+
−
| SATA3.0 differential receive pair 12
+
| rowspan="2" | SATA3.0 differential receive pair 12
 
|-
 
|-
 
| A9
 
| A9
Line 71: Line 65:
 
| B9
 
| B9
 
| SATA1_RX-
 
| SATA1_RX-
−
|
 
−
|
 
 
|-
 
|-
 
| A10
 
| A10
Line 83: Line 75:
 
| A11
 
| A11
 
| SATA3_RX+
 
| SATA3_RX+
−
| SATA2.0 differential receive pair 33
+
| rowspan="2" | SATA2.0 differential receive pair 33
 
| B11
 
| B11
 
| SATA1_TX+
 
| SATA1_TX+
−
| SATA3.0 differential transmit pair 12
+
| rowspan="2" | SATA3.0 differential transmit pair 12
 
|-
 
|-
 
| A12
 
| A12
Line 92: Line 84:
 
| B12
 
| B12
 
| SATA1_TX-
 
| SATA1_TX-
−
|
 
−
|
 
 
|-
 
|-
 
| A13
 
| A13
Line 107: Line 97:
 
| B14
 
| B14
 
| USB3_P
 
| USB3_P
−
| USB Host interface 3
+
| rowspan="2" | USB Host interface 3
 
|-
 
|-
 
| A15
 
| A15
Line 114: Line 104:
 
| B15
 
| B15
 
| USB3_N
 
| USB3_N
−
|
 
 
|-
 
|-
 
| A16
 
| A16
 
| HDA_RST#
 
| HDA_RST#
−
| High Definition Audio
+
| High Definition Audio host reset
−
  host reset
+
 
| B16
 
| B16
 
| USB_OC_2_3#
 
| USB_OC_2_3#
Line 129: Line 117:
 
| B17
 
| B17
 
| USB2_P
 
| USB2_P
−
| USB Host interface 2
+
| rowspan="2" | USB Host interface 2
 
|-
 
|-
 
| A18
 
| A18
Line 136: Line 124:
 
| B18
 
| B18
 
| USB2_N
 
| USB2_N
−
|
 
 
|-
 
|-
 
| A19
 
| A19
Line 154: Line 141:
 
| A21
 
| A21
 
| HDA_SDIN0
 
| HDA_SDIN0
−
| High Definition Audio
+
| High Definition Audio serial host data in0
−
  serial host data in0
+
 
| B21
 
| B21
 
| COM2_TX
 
| COM2_TX
Line 176: Line 162:
 
| A24
 
| A24
 
| USB0_P
 
| USB0_P
−
| USB Host interface lane 0
+
| rowspan="2" | USB Host interface lane 0
 
| B24
 
| B24
 
| LPC_FRAME#
 
| LPC_FRAME#
Line 186: Line 172:
 
| GND
 
| GND
 
| Ground connection
 
| Ground connection
−
|
 
 
|-
 
|-
 
| A26
 
| A26
 
| USB_OC0_1#
 
| USB_OC0_1#
−
| USB Overcurrent Indicator
+
| USB Overcurrent Indicator for lanes 0/1
−
  for lanes 0/1
+
 
| B26
 
| B26
 
| SPI_MISO
 
| SPI_MISO
Line 198: Line 182:
 
| A27
 
| A27
 
| USB1_P
 
| USB1_P
−
| USB Host interface 1
+
| rowspan="2" | USB Host interface 1
 
| B27
 
| B27
 
| SPI_MOSI
 
| SPI_MOSI
Line 207: Line 191:
 
| B28
 
| B28
 
| SPI_CLK
 
| SPI_CLK
−
| SPI interface Clock signal – Reserved for internal use only
+
| SPI interface Clock
−
|
+
 
|-
 
|-
 
| A29
 
| A29
Line 215: Line 198:
 
| B29
 
| B29
 
| SPI_CS1#
 
| SPI_CS1#
−
| SPI interface chip select 1 – Reserved for internal use only
+
| signal –
 
|-
 
|-
 
| A30
 
| A30
 
| LPC_AD0
 
| LPC_AD0
−
| LPC bus multiplexed
+
| rowspan="4" | LPC bus multiplexed command, address and data. Internal PU provided on LPC[3:0]
−
  command, address and data. Internal PU provided on LPC[3:0]
+
 
| B30
 
| B30
 
| SPI_CS0#
 
| SPI_CS0#
−
| SPI interface chip select 0 – Reserved for internal use only
+
| Reserved for internal use only
 
|-
 
|-
 
| A31
 
| A31
Line 230: Line 212:
 
| RESET#
 
| RESET#
 
| Active Low Platform Reset driven by the Host
 
| Active Low Platform Reset driven by the Host
−
|
 
 
|-
 
|-
 
| A32
 
| A32
Line 236: Line 217:
 
| B32
 
| B32
 
| PCIE_CLK+
 
| PCIE_CLK+
−
| Host PCIe CLK output differential pair - 100MHz PCIe Gen2 to PCIe devices
+
| rowspan="2" | Host PCIe CLK output differential pair - 100MHz PCIe Gen2 to PCIe devices
−
|
+
 
|-
 
|-
 
| A33
 
| A33
Line 243: Line 223:
 
| B33
 
| B33
 
| PCIE_CLK-
 
| PCIE_CLK-
−
|
 
−
|
 
 
|-
 
|-
 
| A34
 
| A34
Line 255: Line 233:
 
| A35
 
| A35
 
| PCIE_TX3+
 
| PCIE_TX3+
−
| PCI Express (x1) Gen2 (up
+
| rowspan="2" | PCI Express (x1) Gen2 (up to 5Gbps) differential transmit pair 3
−
  to 5Gbps) differential transmit pair 3
+
 
| B35
 
| B35
 
| PCIE_RX3+
 
| PCIE_RX3+
−
| PCI Express (x1) Gen2 (up to 5Gbps) differential receive pair 3
+
| rowspan="2" | PCI Express (x1) Gen2 (up to 5Gbps) differential receive pair 3
 
|-
 
|-
 
| A36
 
| A36
Line 265: Line 242:
 
| B36
 
| B36
 
| PCIE_RX3-
 
| PCIE_RX3-
−
|
 
−
|
 
 
|-
 
|-
 
| A37
 
| A37
Line 277: Line 252:
 
| A38
 
| A38
 
| PCIE_TX2+
 
| PCIE_TX2+
−
| PCI Express (x1) Gen2 (up to 5Gbps) differential transmit pair 2
+
| rowspan="2" | PCI Express (x1) Gen2 (up to 5Gbps) differential transmit pair 2
 
| B38
 
| B38
 
| PCIE_RX2+
 
| PCIE_RX2+
−
| PCI Express (x1) Gen2 (up to 5Gbps) differential receive pair 2
+
| rowspan="2" | PCI Express (x1) Gen2 (up to 5Gbps) differential receive pair 2
 
|-
 
|-
 
| A39
 
| A39
Line 286: Line 261:
 
| B39
 
| B39
 
| PCIE_RX2-
 
| PCIE_RX2-
−
|
 
−
|
 
 
|-
 
|-
 
| A40
 
| A40
Line 298: Line 271:
 
| A41
 
| A41
 
| PCIE_TX1+
 
| PCIE_TX1+
−
| PCI Express (x1) Gen2 (up to 5Gbps) differential transmit pair 1
+
| rowspan="2" | PCI Express (x1) Gen2 (up to 5Gbps) differential transmit pair 1
 
| B41
 
| B41
 
| PCIE_RX1+
 
| PCIE_RX1+
−
| PCI Express (x1) Gen2 (up to 5Gbps) differential receive pair 1
+
| rowspan="2" | PCI Express (x1) Gen2 (up to 5Gbps) differential receive pair 1
 
|-
 
|-
 
| A42
 
| A42
Line 307: Line 280:
 
| B42
 
| B42
 
| PCIE_RX1-
 
| PCIE_RX1-
−
|
 
−
|
 
 
|-
 
|-
 
| A43
 
| A43
Line 319: Line 290:
 
| A44
 
| A44
 
| PCIE_TX0+
 
| PCIE_TX0+
−
| Host CPU PEG (x1) - PCIe Gen3 (up to 8Gbps) differential transmit pair for external graphics
+
| rowspan="2" | Host CPU PEG (x1) - PCIe Gen3 (up to 8Gbps) differential transmit pair for external graphics
 
| B44
 
| B44
 
| PCIE_RX0+
 
| PCIE_RX0+
−
| Host CPU PEG (x1) - PCIe Gen3 (up to 8Gbps) differential receive pair for external graphics
+
| rowspan="2" | Host CPU PEG (x1) - PCIe Gen3 (up to 8Gbps) differential receive pair for external graphics
 
|-
 
|-
 
| A45
 
| A45
Line 328: Line 299:
 
| B45
 
| B45
 
| PCIE_RX0-
 
| PCIE_RX0-
−
|
 
−
|
 
 
|-
 
|-
 
| A46
 
| A46
Line 340: Line 309:
 
| A47
 
| A47
 
| VCC_12V
 
| VCC_12V
−
| Main 12V power domain
+
| rowspan="4" | Main 12V power domain
 
| B47
 
| B47
 
| VCC_12V
 
| VCC_12V
−
| Main 12V power domain
+
| rowspan="4" | Main 12V power domain
 
|-
 
|-
 
| A48
 
| A48
Line 349: Line 318:
 
| B48
 
| B48
 
| VCC_12V
 
| VCC_12V
−
|
 
−
|
 
 
|-
 
|-
 
| A49
 
| A49
Line 356: Line 323:
 
| B49
 
| B49
 
| VCC_12V
 
| VCC_12V
−
|
 
−
|
 
 
|-
 
|-
 
| A50
 
| A50
Line 363: Line 328:
 
| B50
 
| B50
 
| VCC_12V
 
| VCC_12V
−
|
 
−
|
 
 
|}
 
|}

Latest revision as of 13:29, 6 September 2015

EXT-1 connector HOST side
Pin # Pin Name Signal Description Pin # Pin Name Signal Description
A1 GND Ground connection B1 GND Ground connection
A2 SATA2_TX+ SATA2.0 differential transmit pair 2; Host signal shared with mini PCIe (MUX channel B) B2 SATA0_TX+/CLK+ Host PEG CLK output differential pair - 100MHz PCIe Gen2 to PCIe Graphics device1
A3 SATA2_TX- B3 SATA0_TX-/CLK-
A4 IR_RX IR UART receive signal B4 SATA0_LED SATA activity LED indicator
A5 SATA2_RX+ SATA2.0 differential receive pair 2; Host signal shared with mini PCIe (MUX channel B). Note 3 B5 SATA0_RX+/CLK+ Host PCIe CLK output differential pair - 100MHz PCIe Gen2 to PCIe devices. Note 1
A6 SATA2_RX- B6 SATA0_RX-/CLK-
A7 GND Ground connection B7 V5SBY 5V power domain
A8 SATA3_TX+ SATA2.0 differential transmit pair 33 B8 SATA1_RX+ SATA3.0 differential receive pair 12
A9 SATA3_TX- B9 SATA1_RX-
A10 SMB_ALRT# SMBus Alert used to wake the system B10 DEBUG1 Reserved debug signal
A11 SATA3_RX+ SATA2.0 differential receive pair 33 B11 SATA1_TX+ SATA3.0 differential transmit pair 12
A12 SATA3_RX- B12 SATA1_TX-
A13 V5SBY 5V power domain B13 V5SBY 5V power domain
A14 SMB_CLK SMBus host clock output. Connect to SMBus slave. B14 USB3_P USB Host interface 3
A15 SMB_DAT SMBus bidirectional data. Connect to SMBus slave. B15 USB3_N
A16 HDA_RST# High Definition Audio host reset B16 USB_OC_2_3# USB Overcurrent Indicator for lanes 2/3
A17 HDA_SYNC High Definition Audio host sync B17 USB2_P USB Host interface 2
A18 HDA_BITCLK High Definition Audio host bit clock out 24MHz B18 USB2_N
A19 HDA_SDOUT High Definition Audio serial host data out B19 V5SBY 5V power domain
A20 HDA_SDIN1 High Definition Audio serial host data in1 B20 COM2_RX For internal test purposes
A21 HDA_SDIN0 High Definition Audio serial host data in0 B21 COM2_TX For internal test purposes
A22 DEBUG3 Reserved debug signal B22 LPC_SERIRQ Serial Interrupt Request
A23 GND Ground connection B23 LPC_CLK Single Ended 33MHz CLK host out to PCI devices
A24 USB0_P USB Host interface lane 0 B24 LPC_FRAME# LPC interface frame signal
A25 USB0_N B25 GND Ground connection
A26 USB_OC0_1# USB Overcurrent Indicator for lanes 0/1 B26 SPI_MISO SPI interface MISO signal – Reserved for internal use only
A27 USB1_P USB Host interface 1 B27 SPI_MOSI SPI interface MOSI signal – Reserved for internal use only
A28 USB1_N B28 SPI_CLK SPI interface Clock
A29 GND Ground connection B29 SPI_CS1# signal –
A30 LPC_AD0 LPC bus multiplexed command, address and data. Internal PU provided on LPC[3:0] B30 SPI_CS0# Reserved for internal use only
A31 LPC_AD1 B31 RESET# Active Low Platform Reset driven by the Host
A32 LPC_AD2 B32 PCIE_CLK+ Host PCIe CLK output differential pair - 100MHz PCIe Gen2 to PCIe devices
A33 LPC_AD3 B33 PCIE_CLK-
A34 GND Ground connection B34 EXT_PRSNT# Clock Request for PCI Express 100 MHz Clocks
A35 PCIE_TX3+ PCI Express (x1) Gen2 (up to 5Gbps) differential transmit pair 3 B35 PCIE_RX3+ PCI Express (x1) Gen2 (up to 5Gbps) differential receive pair 3
A36 PCIE_TX3- B36 PCIE_RX3-
A37 PCIE_WAKE# PCI Express Wake Event from Device to Host B37 SPI_EXT_CNTRL SPI interface external control signal
A38 PCIE_TX2+ PCI Express (x1) Gen2 (up to 5Gbps) differential transmit pair 2 B38 PCIE_RX2+ PCI Express (x1) Gen2 (up to 5Gbps) differential receive pair 2
A39 PCIE_TX2- B39 PCIE_RX2-
A40 GND Ground connection B40 GND Ground connection
A41 PCIE_TX1+ PCI Express (x1) Gen2 (up to 5Gbps) differential transmit pair 1 B41 PCIE_RX1+ PCI Express (x1) Gen2 (up to 5Gbps) differential receive pair 1
A42 PCIE_TX1- B42 PCIE_RX1-
A43 PWRBTN# System power button signal B43 SLP# Assert LP state S3 (sleep) active low signal
A44 PCIE_TX0+ Host CPU PEG (x1) - PCIe Gen3 (up to 8Gbps) differential transmit pair for external graphics B44 PCIE_RX0+ Host CPU PEG (x1) - PCIe Gen3 (up to 8Gbps) differential receive pair for external graphics
A45 PCIE_TX0- B45 PCIE_RX0-
A46 RESERVED Reserved debug signal B46 RESERVED Reserved debug signal
A47 VCC_12V Main 12V power domain B47 VCC_12V Main 12V power domain
A48 VCC_12V B48 VCC_12V
A49 VCC_12V B49 VCC_12V
A50 VCC_12V B50 VCC_12V
Retrieved from "https://fit-pc.com/wiki/index.php?title=Template:EXT1_connector_HOST_side_pinout&oldid=3023"