Changes

Jump to: navigation, search

Fitlet1 FACET Cards

1,340 bytes added, 08:19, 9 September 2015
FACET PCB design should meet mini PCI Express design guidelines in terms of edge connector design (hard gold fingers), PCB thickness, other parameters, and follow general recommendations described in PCI express mini card electromechanical specification 1.2.
 
 
=== Extended Functionality ===
 
'''PCI Express Interface'''
Fitlet-X SoC provides several PCI Express Root Ports, supporting the PCI Express Base Specification, Revision 2.0. Each Root Port lane supports up to 5 Gbps bandwidth in each direction (10 Gbps concurrent). FACET PCI Express interface consist of 3x PCI Express gen2.0 lanes.
 
'''LPC Bus Interface'''
The Low Pin Count (LPC) bus interface is a cost-efficient, low-speed interface designed to support low-speed legacy (ISA, X-bus) devices. The LPC interface essentially eliminates the need of ISA and X-bus in the system. Here the ISA bus is internal to SoC and is used for connecting to the legacy Direct Memory Access (DMA) logic. The LPC host controller is integrated into the SoC. It connects to the internal A-Link bus on one side and the LPC and Serial Peripheral Interface (SPI) buses on the other side. The ISA interface is only used for legacy DMA operation.
Examples of LPC devices include Super I/O (disk controller, keyboard controller), BIOS RAM, audio, Trusted Platform Module (TPM), and system management controller.
LPC host controller has the A-Link bus on one side and the LPC bus on the other. The host controller supports memory and I/O read/write, DMA read/write, and bus master memory I/O read/write. It supports up to two bus masters and seven DMA channels
1,916
edits