Changes
/* FACET Card Electrical Interface */
| Clock request - open drain, active low driven by mini PCIe card to request PCIe reference clock
| 8
| UIM_PWR/ReservedLAD0| rowspan="54" | The UIM LPC Bus Data signals are defined on the system connector to provide the interface between the removable User Identity Module (UIM) Interface - an extension of SIM and WWAN.
|-
| 9
| Ground connection
| 10
| UIM_DATA/ReservedLAD1
|-
| 11
| rowspan="2" | Reference clock used to assist the synchronization of PCI Express interface timing circuits
| 12
| UIM_CLK/ReservedLAD2
|-
| 13
| REFCLK+
| 14
| UIM_RESET/ReservedLAD3
|-
| 15
| Ground connection
| 16
| UIM_VPP/ReservedLFRAME#| LPC Bus frame signal. Active Low
|-
| colspan="6" style="text-align: center; font-weight: bold;" | Mechanical Notch Key
|-
| 37
| GNDLPC_CLK0| Ground connectionLPC Bus clock
| 38
| USB_D+
| 3.3V power rail
| 42
| LED_WWAN# / LPC_SMI#| rowspan="3" | Active low output signals are provided to allow status indications to users via system provided LEDs(or LPC Bus control signals)
|-
| 43
| rowspan="2" | <span style="color:#FF0000">PCI Express Gen2 differential transmit pair 1</span>
| 44
| LED_WLAN# / LPC_PME#
|-
| 45
| <span style="color:#FF0000">PETp1</span>
| 46
| LED_WPAN#/ SERIRQ
|-
| 47
| ReservedLPC_RST#| tbdLPC Bus Reset signal. Active Low
| 48
| 1.5V
