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FACE Modules:FM-OPLN

800 bytes removed, 09:23, 27 December 2016
=== Block Diagram ===
[[File:FM-XTDEU2_4.png]]
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=== Hardware Specifications ===
The following section provides information about FM-XTDEU2/4 main components and features.
'''Realtek RTL8111F Intel I210IS GbE Controller'''The Realtek RTL8111F Gigabit Intel Ethernet I210 controller combines is a single port, compact, low power component that supports GbE designs. The I210 offers a triplefully-speed IEEE 802.3 compliant integrated GbE Media Access Controller Control (MAC) with a triple-speed Ethernet transceiver, PCI Express bus controller, Physical Layer (PHY) port and embedded memory. With state-of-the-art DSP technology and mixed-mode signal technology, the RTL8111F offers high-speed transmission over CAT 5 UTP cable. The RTL8111F supports PCI Express 2.1(5GT/s).1 bus interface The I210 enables 1000BASE-T implementations using an integrated PHY. It can be used for host communications with power managementserver system configurations such as rack mounted or pedestal servers, and is compliant with the IEEE 802in an add-on NIC or LAN on Motherboard (LOM) design.3u specification Another possible system configuration is for 10/100Mbps Ethernet and the IEEE 802.3ab specification for 1000Mbps Ethernetblade servers as a LOM or mezzanine card. It can also supports an auxiliary power auto-detect function, and will auto-configure related bits of the PCI power management registers be used in PCI configuration space. The RTL8111F features embedded Oneapplications such as switch add-Time-Programmable (OTP) memory to replace the external EEPROMon cards and network appliances.Advanced Configuration Power management Interface (ACPI) – power management for modern operating systems that are capable of Operating System-directed Power Management (OSPM) – One independent interface is supported used to achieve connect the most efficient power management possibleI210 port to external devices. In addition to the ACPI feature, remote Wake on LAN The following protocol is supported in both ACPI and APM : MDI (Advanced Power Managementcopper) environmentssupport for standard IEEE 802. The RTL8111F is suitable 3 Ethernet interface for multiple market segments 1000BASE-T, 100BASE-TX, and emerging 10BASE-T applications(802.3, such as desktop, mobile802.3u, workstation, server, communications platforms and embedded applications802.3ab).
'''Main Features'''
*Integrated 10/100/1000 transceiver*Auto-Negotiation with Next Page capability*Supports PCI Express 1PCIe v2.1*Supports pair swap(5 GT/polarity/skew corrections) x1, with Switching Voltage Regulator (iSVR)*Crossover Detection & AutoIntegrated Non-Correction*Wake-on-LAN and remote wake-up support*Supports Full Duplex flow control Volatile Memory (IEEE 802.3xiNVM)*Supports jumbo frame to 9K bytesPlatform Power Efficiency*Fully compliant with IEEE 802.3, IEEE 802.3u, IEEE 802.3ab*Supports IEEE 802.1P Layer 2 Priority Encoding*Supports IEEE 802.1Q VLAN tagging*Supports IEEE 802.3az-2010 Energy Efficient Ethernet (EEE)*Embedded OTP memory can replace the external EEPROMProxy: ECMA-393 and Windows logo for proxy offload*Supports power down/link down power saving/PHY disable modeJumbo frames*BuiltInterrupt moderation, VLAN support, IP checksum offload* RSS and MSI-X to lower CPU utilization in switching regulatormulti-core systems*Supports Customized LEDs*Supports 1Advanced cable diagnostics, auto MDI-Lane 2.5Gbps PCI Express BusX*Supports hardware ECC (Error Correction Code) function– error correcting memory in packet buffers*Supports hardware CRC Four Software Definable Pins (Cyclic Redundancy CheckSDPs) function*48-pin QFN ‘Green’ package
'''IDT ICS9DB102 Pericom PI6C20400 1-to-2 4 Differential Clock Driver'''IDT ICS9DB102 Pericom Semiconductor's PI6C20400 is two output a high-speed, low-noise differential clock driver/buffer for PCIe Gen1 & Gen2 compatible with CML and HCSL current mode differential outputsI/O technology.Device zero-delay buffer supports PCI Express clocking requirements. The ICS9DB102 is driven by device distributes a differential compliant input clock. It attenuates jitter on the input clock and has a selectable PLL Band Width to maximize performance in systems four differential pairs of clock outputs either with or without Spread-Spectrum clockingPLL. The clock outputs are controlled by input selection of several static control signals and Host SMBus interface. The device oriented and designed for PCI Express applications.-->
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