Changes

IDT ICS9DB102 is two output clock buffer for PCIe Gen1 & Gen2 with HCSL current mode differential outputs.

Device zero-delay buffer supports PCI Express clocking requirements. The ICS9DB102 is driven by a differential compliant input clock. It attenuates jitter on the input clock and has a selectable PLL Band Width to maximize performance in systems with or without Spread-Spectrum clocking.

=== Schematics ===

=== Layout ===

=== Mechanical ===

=== Assembly ===

=== SW Drivers ===