EXT-2 connector HOST side
|
Pin #
|
Pin Name
|
Signal Description
|
Pin #
|
Pin Name
|
Signal Description
|
A1
|
GND
|
Ground connection
|
B1
|
GND
|
Ground connection
|
A2
|
PEG_RX0+/RSVD0
|
Host CPU PEG_0 (x8) - PCIe Gen3 (up
to 8Gbps) differential receive pair for external graphics 1
|
B2
|
PEG_TX0+/RSVD6
|
Host CPU PEG_0 (x8) - PCIe Gen3 (up
to 8Gbps) differential transmit pair for external graphics 1
|
A3
|
PEG_RX0-/RSVD1
|
B3
|
PEG_TX0-/RSVD7
|
A4
|
DGPU_PRSNT#/RSVD3
|
Host chipset GPIO67, Input, PU-10k
|
B4
|
DGPU_PWREN#/RSVD8
|
Host chipset GPIO54, Output, PU-8.2k
|
A5
|
PEG_RX1+/RSVD4
|
Host CPU PEG_1 (x8) - PCIe Gen3 (up
to 8Gbps) differential receive pair for external graphics 1
|
B5
|
PEG_TX1+/RSVD9
|
Host CPU PEG_1 (x8) - PCIe Gen3 (up
to 8Gbps) differential transmit pair for external graphics 1
|
A6
|
PEG_RX1-/RSVD5
|
B6
|
PEG_TX1-/RSVD10
|
A7
|
GND
|
Ground connection
|
B7
|
GND
|
Ground connection
|
A8
|
PEG_RX2+/RSVD11
|
Host CPU PEG_2 (x8) - PCIe Gen3 (up
to 8Gbps) differential receive pair for external graphics 2
|
B8
|
PEG_TX2+/RSVD16
|
Host CPU PEG_2 (x8) - PCIe Gen3 (up
to 8Gbps) differential transmit pair for external graphics 2
|
A9
|
PEG_RX2-/RSVD12
|
B9
|
PEG_TX2-/RSVD17
|
A10
|
DGPU_PWROK/RSVD13
|
Host chipset GPIO17, Input/Output,
PD-10k
|
B10
|
DGPU_HOLD_RST#/RSVD18
|
Host chipset GPIO50, Output, PU-8.2k
|
A11
|
PEG_RX3+/RSVD14
|
Host CPU PEG_3 (x8) - PCIe Gen3 (up
to 8Gbps) differential receive pair for external graphics 2
|
B11
|
PEG_TX3+/RSVD19
|
Host CPU PEG_3 (x8) - PCIe Gen3 (up
to 8Gbps) differential transmit pair for external graphics 2
|
A12
|
PEG_RX3-/RSVD15
|
B12
|
PEG_TX3-/RSVD20
|
A13
|
GND
|
Ground connection
|
B13
|
GND
|
Ground connection
|
A14
|
PEG_RX4+/RSVD21
|
Host CPU PEG_4 (x8) - PCIe Gen3 (up
to 8Gbps) differential receive pair for external graphics 2
|
B14
|
PEG_TX4+/RSVD26
|
Host CPU PEG_4 (x8) - PCIe Gen3 (up
to 8Gbps) differential transmit pair for external graphics 2
|
A15
|
PEG_RX4-/RSVD22
|
B15
|
PEG_TX4-/RSVD27
|
A16
|
DGPU_SELECT#/RSVD23
|
Host chipset GPIO52, Output, PU-8.2k
|
B16
|
DGPU_HPD_INTR#/RSVD28
|
Host chipset GPIO6, Input, PU-10k
|
A17
|
PEG_RX5+/RSVD24
|
Host CPU PEG_5 (x8) -
PCIe Gen3 (up to 8Gbps) differential receive pair for external graphics 2
|
B17
|
PEG_TX5+/RSVD29
|
Host CPU PEG_5 (x8) -
PCIe Gen3 (up to 8Gbps) differential transmit pair for external graphics 2
|
A18
|
PEG_RX5-/RSVD25
|
B18
|
PEG_TX5-/RSVD30
|
A19
|
V5SBY
|
5V power domain
|
B19
|
V5SBY
|
5V power domain
|
A20
|
PEG_RX6+/RSVD31
|
Host CPU PEG_6 (x8) - PCIe Gen3 (up
to 8Gbps) differential receive pair for external graphics 2
|
B20
|
PEG_TX6+/RSVD36
|
Host CPU PEG_6 (x8) -
PCIe Gen3 (up to 8Gbps) differential transmit pair for external graphics 2
|
A21
|
PEG_RX6-/RSVD32
|
B21
|
PEG_TX6-/RSVD37
|
A22
|
DGPU_PWM_SELECT#/RSVD33
|
Host chipset GPIO53, Output, No pull
|
B22
|
SPARE/eDP_HDP
|
NC
|
A23
|
PEG_RX7+/RSVD34
|
Host CPU PEG_7 (x8) - PCIe Gen3 (up
to 8Gbps) differential receive pair for external graphics 2
|
B23
|
PEG_TX7+/RSVD38
|
Host CPU PEG_7 (x8) -
PCIe Gen3 (up to 8Gbps) differential transmit pair for external graphics 2
|
A24
|
PEG_RX7-/RSVD35
|
B24
|
PEG_TX7-/RSVD39
|
A25
|
GND
|
Ground connection
|
B25
|
GND
|
Ground connection
|
A26
|
LVDS_A0+/eDP_TX0+
|
LVDS Channel A
differential pair 0 Host data output 3
|
B26
|
PEG_CLK+/RSVD40
|
Host PEG CLK output
differential pair - 100MHz PCIe Gen2
to PCIe Graphics device
|
A27
|
LVDS_A0-/eDP_TX0-
|
B27
|
PEG_CLK-/RSVD41
|
A28
|
LVDS_A1+/eDP_TX1+
|
LVDS Channel A
differential pair 1 Host data output 3
|
B28
|
LVDS_BKLT_CTRL
|
Panel Backlight
Brightness Control 3
|
A29
|
LVDS_A1-/eDP_TX1-
|
B29
|
COM1_DCR
|
Full RS232 interface from Host to DCE device
|
A30
|
LVDS_A2+/eDP_TX2+
|
LVDS Channel A
differential pair 2 Host data output 3
|
B30
|
COM1_TX
|
A31
|
LVDS_A2-/eDP_TX2-
|
B31
|
COM1_DCD
|
A32
|
GND
|
Ground connection
|
B32
|
GND
|
Ground connection
|
A33
|
LVDS_A3+/eDP_TX3+
|
LVDS Channel A
differential pair 3 Host data output 3
|
B33
|
COM1_DTR
|
Full RS232 interface from
Host to DCE device
|
A34
|
LVDS_A3-/eDP_TX3-
|
|
B34
|
COM1_RTS
|
A35
|
LVDS_VDD_EN
|
LVDS Panel Power Enable 3
|
B35
|
COM1_RX
|
A36
|
LVDS_ACLK+/eDP_AUX+
|
LVDS Channel A
differential pair Host clock output 3
|
B36
|
COM1_CTS
|
A37
|
LVDS_ACLK-/eDP_AUX-
|
|
B37
|
COM1_RI
|
A38
|
GND
|
Ground connection
|
B38
|
LVDS_BKLT_EN
|
LVDS Backlight Enable 3
|
A39
|
LVDS_CTRL_CLK
|
LVDS Control interface
for external SSC clock chip (I2C based). Optional. 3
|
B39
|
LVDS_I2C_CLK
|
LVDS DDC (I2C based)
management interface. EDID support for flat panel display 3
|
A40
|
LVDS_CTRL_DATA
|
|
B40
|
LVDS_I2C_DAT
|
|
A41
|
PEG_CLK_REQ#/RSVD42
|
Clock Request Signal for
PCIe Graphics (PEG)
|
B41
|
GND
|
Ground connection
|
A42
|
RESERVED
|
Reserved
|
B42
|
RESERVED
|
Reserved
|
A43
|
RESERVED
|
B43
|
RESERVED
|
A44
|
GND
|
Ground connection
|
B44
|
NC
|
NC
|
A45
|
RESERVED
|
Reserved
|
B45
|
RESERVED
|
Reserved
|
A46
|
RESERVED
|
B46
|
RESERVED
|
A47
|
USB_OC_4_5#
|
USB Overcurrent Indicator
for lanes 2/3
|
B47
|
SPARE0
|
Host chipset spare GPIO
|
A48
|
USB4_P
|
USB Host interface 4
|
B48
|
VCC_12V
|
Main 12V power domain
|
A49
|
USB4_N
|
B49
|
VCC_12V
|
A50
|
GND
|
Ground connection
|
B50
|
VCC_12V
|