fit-pc2 z510 with two thread support
Posted: Sun Sep 15, 2013 1:59 am
I think that the M2 bios for the fit-pc2 was written for 2G memory machines, and it implicitly sets the z5xx cpu up for hyperthreading. Hyperthreading is extremely useful, and I am writing this from a non-Compulab z510 with hyperthreading enabled (see below). My experience using a two-thread z510 is that it does streaming video much better than does the Compulab z510, which is not set up for two-thread hyperthreads. If there is some way to install the M2 bios on the fit-pc2 z510, assuming it sets up the cpu for hyperthreading as below, I'd be willing to volunteer to do it as an experiment. For one thing, the peacekeeper benchmark on RIP goes up from 370 on the Compulab to 420 on this machine. And, full-screen flash video loses the frame-by-frame effect on the Compulab z510 and goes to nearly continuous with lip synchronization. Please contact me at my personal email address.
This is what the lshw program shows for the z510 system that I am writing this from:
*-cpu
description: CPU
product: Intel(R) Atom(TM) CPU Z510 @ 1.10GHz
vendor: Intel Corp.
physical id: 4
bus info: cpu@0
version: 6.12.2
serial: 0001-06C2-0000-0000-0000-0000
slot: CPU 1
size: 1100MHz
capacity: 1100MHz
width: 32 bits
clock: 100MHz
capabilities: boot fpu fpu_exception wp vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe nx constant_tsc arch_perfmon pebs bts aperfmperf pni dtes64 monitor ds_cpl vmx est tm2 ssse3 xtpr pdcm movbe lahf_lm dtherm tpr_shadow vnmi flexpriority cpufreq
configuration: cores=1 enabledcores=1 id=0 threads=2
*-cache:0
description: L1 cache
physical id: 5
slot: L1-Cache
size: 24KiB
capacity: 24KiB
capabilities: internal write-back data
*-cache:1
description: L2 cache
physical id: 6
slot: L2-Cache
size: 512KiB
capacity: 512KiB
capabilities: internal write-back unified
*-logicalcpu:0
description: Logical CPU
physical id: 0.1
width: 32 bits
capabilities: logical
*-logicalcpu:1
description: Logical CPU
physical id: 0.2
width: 32 bits
capabilities: logical
This is what the lshw program shows for the z510 system that I am writing this from:
*-cpu
description: CPU
product: Intel(R) Atom(TM) CPU Z510 @ 1.10GHz
vendor: Intel Corp.
physical id: 4
bus info: cpu@0
version: 6.12.2
serial: 0001-06C2-0000-0000-0000-0000
slot: CPU 1
size: 1100MHz
capacity: 1100MHz
width: 32 bits
clock: 100MHz
capabilities: boot fpu fpu_exception wp vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe nx constant_tsc arch_perfmon pebs bts aperfmperf pni dtes64 monitor ds_cpl vmx est tm2 ssse3 xtpr pdcm movbe lahf_lm dtherm tpr_shadow vnmi flexpriority cpufreq
configuration: cores=1 enabledcores=1 id=0 threads=2
*-cache:0
description: L1 cache
physical id: 5
slot: L1-Cache
size: 24KiB
capacity: 24KiB
capabilities: internal write-back data
*-cache:1
description: L2 cache
physical id: 6
slot: L2-Cache
size: 512KiB
capacity: 512KiB
capabilities: internal write-back unified
*-logicalcpu:0
description: Logical CPU
physical id: 0.1
width: 32 bits
capabilities: logical
*-logicalcpu:1
description: Logical CPU
physical id: 0.2
width: 32 bits
capabilities: logical